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Maxim Levit

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Dr. Maxim Levit has earned his B.Sc. and M.Sc. in Physics and Metallurgy from Polytechnic Institute in St. Petersburg, Russia, and received his Ph.D. in Materials Science from the Technion – Israel Institute of Technology. Dr. Levit joined Intel in 1997 as Quality and Reliability (Q&R) engineer and since then he has held several technical and managerial positions in the areas of Q&R, VLSI circuit design, VLSI product debug and VLSI packaging. In the recent years Dr. Levit serves as a director of Client CPU Quality and Reliability department. Dr. Levit started his teaching carrier as an adjunct teacher at the Technion-IIT in 2000, and since then he was teaching courses of Physics and Reliability of VLSI devices, Packaging of modern VLSI devices and Semiconductor devices. In 2020 Dr. Maxim Levit joined GTIIT as a senior adjunct teacher. Dr. Levit areas of academic interest include transistor reliability, VLSI device and VLSI package failure mechanisms, Electro-migration, ESD, Latch-Up, transistor aging effects and reliability modeling. Dr. Levit is an author of 6 patents and numerical academic papers and talks. Dr. Maxim Levit is married and has 3 children. Besides work Dr. Maxim Levit spends his time with family on outdoor activities and most recently he enjoys playing with his 2 grandchildren.

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